彰化師大雲端學院

彰師大雲端學院

1102-Design of Central Processing Unit-53030

Registration：Now ~ Any Time
Course Period：2022-02-01 ~ 2022-07-01

Course Introduction

Pass condition

Grade：60 Fraction

Introducton_processor_design_20220222

run_first_verilog_example

verilog2017_1(20200303)

verilog2017_2(20100315)

verilog2017_3(20110301)

verilog2017_3(20170413)

verilog2017_4(20090413)

verilog2017_5(20100426)

MIPS_R2000_ppt

MIPS_simulator_SPIM_20210526

MIPSR2000_ChenChengEn

MIPSR2000_ChenKungEou

MIPSR2000_LinChiWha

MIPSR2000_WhuWenChing

期末專題20220601

Course Introduction

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Instructor

張孟洲

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