Pass condition
Grade:60 Fraction
  • 02-96CMOS Process Flow Introducrtion_CICv18-3
  • 02-96CMOS Process Flow Introducrtion_CICv18-2
  • 02-96CMOS Process Flow Introducrtion_CICv18-1
  • 02-96CMOS Process Flow Introducrtion
  • 03-Design Rule
  • 04-96-Analog Layout consideration20111115
  • 05-Layout of MOS Transistor_CICv18
  • 03-Design Rule20190924-1
  • 03-Design Rule20190924-2
  • 04-96-Analog Layout consideration20190924-3
  • 01-99Workstation_for_cic18
  • 101a_eval.sp
  • CIC_inv3.3
  • 05-Layout of MOS Transistor_20191015-1
  • 09-Layout of OPA_CICv18
  • 09-Layout of OPA_CICv1820191029-1
  • 08-DAC-layout_CICv18
  • 10-Layout of current cell_CICv18
Instructor
陳勛祥
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